The present invention relates in general to semiconductor device packaging architectures and, in more particular, to techniques adaptable for effective use in large capacity accommodatable semiconductor devices with a plurality of chips mounted together in a single package structure.
Investigation made by the inventors as named herein has revealed that currently available techniques for achieving increased storage capacities in modern memory package structures with multiple chips mound together in a single package may include, but not limited to, a scheme for stacking or laminating a plurality of chips in a direction along the thickness of a package, and a scheme for disposing a plurality of chips in a direction along a plane. Examples of the latter scheme are disclosed, for example, in Japanese Patent Laid-Open Nos. 17099/1999 and 256474/1998, wherein the techniques as taught by these Japanese printed publications are generally arranged as will be set forth below.
The prior known technique as taught by Japanese Patent Laid-Open No. 17099/1999 is directed to a package structure including a rectangular module substrate with four bare chips mounted thereon. The module substrate has a surface on which a linear array of conductive pads is formed at part near or around the central portion along the long sides thereof while letting chip pairs be mounted on the chip surface on the opposite sides of the pad array. Each bare chip is structurally designed to have bonding pads that are aligned in a linear array extending along the center line thereof, wherein these bonding pads and those pads on the module substrate are connected together by use of bonding wires with a resin material deposited to cover the bare chips and bonding wires.
The prior art technique suggested from Japanese Patent Laid-Open No. 256474/1998 is such that multiple bare chips are mounted on the top and bottom surfaces of a module substrate, each of which chips has a layout of center pads capable of permitting connection of wires extending from the chip center toward lateral directions, thereby providing a structure that uses bonding wires to electrically connect together bonding pads on each bare chip and the pads on the module substrate.
After consideration given to the above-identified Japanese documents, the inventors wish to make the following observations about the prior art approaches as taught thereby.
The prior art technique of Japanese Patent Laid-Open No. 17099/1999 is based on the fact that addressing terminals are useable in common among four separate chips while simultaneously enabling common use or xe2x80x9ccommonizationxe2x80x9d of control terminals including write-enable terminals and chip-enable terminals and the like, for disposing those on-substrate pads to be connected to these commonly useable or xe2x80x9ccommnizeablexe2x80x9d terminals in the form of a linear array at a location in close proximity to the central part on the substrate, wherein this prior art fails to involve any specific teachings about how function assignment is done to respective on-substrate pads and to respective onchip pads.
The prior art of Japanese Patent Laid-Open No. 256474/1998 is inherently designed so that on-substrate chips coupled to common signals among a plurality of chipsxe2x80x94such as address signals, control signals, power supply, or the likexe2x80x94are provided on the substrate in areas lying between adjacent ones of the chips mounted thereon to thereby provide connectivity of two bonding wires from both chips to these interchip pads, wherein this prior art is not stated about any exact schemes for assigning functions to respective on-substrate pads and also to onchip pads.
The present invention has been made in view of the need for function assignment to on-substrate/onchip pads such as the ones stated supra, and a primary object of the invention is to provide a new and improved semiconductor device capable of improving flexibilities of forming a pattern of electrical leads(wirings) used for electrical connection from chips via a substrate up to external terminals, by uniquely arranging the layout of addressing pads of those address signals as commonly used among four chips and also substrate structure and others.
The said and other objects, features and advantages of this invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.
A brief summary of some representative ones of the inventions as disclosed herein will be explained below.
The present invention is adaptable for use in a semiconductor device that includes four chips each having on its surface a memory circuit and a plurality of pads including a plurality of address pads for use in inputting address signals of the memory circuit along with a plurality of input/output pads for inputting and outputting input/output data and also having a pair of long sides and a pair of short sides, a substrate supporting thereon the four chips and having on its surface a plurality of pads including address pads and input/output pads as electrically connected to respective ones of the address pads and input/output pads of the four chips, and a plurality of external terminals being electrically connected to the address pads and input/output pads on the substrate and including address terminals and input/output terminals as provided on a bottom surface of the substrate, which device offers specific features which follow.
More specifically the semiconductor device of this invention is characterized in that the four chips are disposed on the substrate in form of an array of rows and columns, the plurality of address pads of each of the four chips are disposed adjacent to one side of the pair of short sides, the plurality of input/output pads are disposed and spaced apart from one side of the pair of short sides toward the other side of the pair of short sides when compared to the plurality of address pads, one of the pair of short sides of each of the four chips is disposed adjacent to one of the pair of short sides of its neighboring chip to permit the plurality of address pads of each of the four chips are placed at central part on a plane of the substrate, corresponding pads in the plurality of address pads of each of the four chips are commonly connected together to the address terminals of the external terminals, and the plurality of input/output pads of each of the four chips are connected to the input/output terminals of the external terminals independently of one another in units of respective chips. With such an arrangement, it becomes possible to improve the degree of freedom or flexibility in arranging electrical wiring leads in connection between the pads on each chip and the external terminals.
In this arrangement, in order to further improve the lead wiring flexibility, the device is featured in that the substrate is of a polygonal shape having a pair of long sides and a pair of short sides, the substrate has a multilayered wiring lead structure with electrical leads of a plurality of layers, the four chips are laid out into a matrix of two rows in a direction along the short sides of the substrate and two columns in a long side direction, address pads of chips laid out in the short side direction of the substrate are electrically connected together by a first lead layer extending in the short side direction of the substrate, and address pads of chips laid out in the long side direction of the substrate are electrically connected together by a second lead layer being different from the first lead layer and extending in the long side direction of the substrate. This first lead layer is an uppermost layer among the plurality of lead layers of the substrate whereas the second lead layer is a lowermost layer among the plurality of lead layers of the substrate, wherein the first lead layer and the second lead layer are electrically connected together by more than one through-hole filled with a conductive material as formed in the substrate; further, the external terminals have lands used for connection of solder balls, the second lead layer is the same in level as the lands of the external terminals, and all of the lands of the external terminals are disposed on a bottom surface of the substrate in an area outside of the second lead layer.
Furthermore, in regard to the layout of the external terminals at the substrate, in order to create modules, the substrate is arranged in form of a rectangular shape, wherein the address terminals of the external terminals are laid out at central part of a pair of long sides of this substrate of rectangular shape, while letting the input/output terminals of the external terminals be disposed at corner portions of the substrate. Moreover, more than one control pad for use in inputting a control signal of the memory circuit is further provided on each chip, one of each pair of short sides of the four chips is disposed adjacent to a corresponding one of its neighboring chip to permit each control pad on each chip to be placed on a center side on the plane of the substrate, each control pad is commonized and connected to a control terminal of the external terminals, and the control terminal is disposed at central part of a long side of the substrate.
In addition, regarding each chip, for purposes of enabling common use or xe2x80x9ccommonizationxe2x80x9d of address signals, the pads on each chip are laid out into a linear array along a long side direction of each chip at central part thereof; or alternatively, the pads on each chip are laid out along the pair of long sides of each chip.
In addition, regarding the pads on the substrate, for purposes-of readily performing wire bonding, the pads on each chip are disposed along outside of the pair of long sides of each chip.
With regard to practically implementable package structure, each chip is mounted on the substrate via a die-bonding material, the pads on each chip are connected by bonding wires to the pads on the substrate, each chip mounted on the substrate and the bonding wires are structurally arranged to be molded by a resin material, and the substrate is provided with a penetration hole for permitting escape of moisture vapor occurring due to thermal processing during solder reflow processes, wherein a step-like surface configuration correcting member made of a dielectric material is disposed at peripheral part of the penetration hole of the substrate while letting the die-bonding material be prevented from being disposed at the periphery of the penetration hole of the substrate.
Regarding other possible practical package structure, each chip is mounted on the substrate by a face-down structure, and each chip and the substrate are coupled together by flip chip bonding techniques using metallic balls to have a structure with a resin material filled between a surface of each chip and the substrate.
This invention also provides another semiconductor device which is featured in that four chips are disposed in a linear symmetrical fashion on the substrate in form of an array of rows and columns, the plurality of address pads of each of the four chips are disposed adjacent to one side of the pair of short sides, the plurality of input/output pads are disposed and spaced apart from one side of the pair of short sides toward the other side of the pair of short sides when compared to the plurality of address pads, one of the pair of short sides of each of the four chips is disposed adjacent to one of the pair of short sides of its neighboring chip to permit the plurality of address pads of each of the four chips are placed at central part on a plane of the substrate, corresponding pads in the plurality of address pads of each of the four chips are commonly connected together to the address terminals of the external terminals, and the plurality of input/output pads of each of the four chips are connected to the input/output terminals of the external terminals independently of one another in units of respective chips. With such an arrangement, it is possible by using the linear-symmetrical chip layout to attain commonization of address signals while at the same time improving the flexibility in wiring leads in connection between pads on each chip and the external terminals.
The invention also provides yet another semiconductor device which is featured in that four chips are each such that the input/output pads are of xc3x9716 input/output bit configuration, corresponding pads in respective plurality of address pads of each of the four chips are connected in common to the address terminals of the external terminals, and the plurality of input/output pads of each of the four chips are connected to said input/output terminals of the external terminals in a way independent per each chip and are thus caused by the four chips to have xc3x9764 input/output bit configuration. With such an arrangement, it is possible by using four chips of xc3x9716 input/output bit configuration to make up the intended package with xc3x9764 input/output bit configuration.
Further, as per each chip and the substrate, for the purpose of arranging the package with either xc3x9764 or xc3x9732 input/output bit configuration, the four chips are each designed to have an option-use pad with a bonding option function capable of permitting the input/output bit configuration to switch between xc3x9716 and xc3x978, wherein the substrate has an option-use pad with a bonding option function capable of letting the input/output bit configuration switch between xc3x9716 and xc3x978, switching between the option-use pad on each said chip and the option-use pad on the substrate allows each of the four chips to exhibit either xc3x9716- or xc3x978-input/output bit configurations, and xc3x9764- or xc3x9732-input/output bit configurations is established by the four chips.
Additionally, the semiconductor device incorporating the principles of the invention should not be limited only to the memory circuit, and a further semiconductor device may be provided which includes specified circuitry, a chip having on its surface a plurality of pads for use in inputting and outputting respective signals of the circuitry, and a substrate having on its surface a plurality of pads being electrically connected to the pads on the chip respectively, and a plurality of external terminals as electrically connected to the pads on the substrate respectively, characterized in that the pads on the chip and the pads on the substrate are structurally arranged so that they are connected together by bonding wires, that first bonding is performed to the pads on the substrate, and that second bonding is done to the pads on the chip. This may be effective when improving distance margins between chips and bonding wires while suppressing the height of bonding wires.
Furthermore, as per the on-chip pads, in order to prevent damages to chips, metal balls are preformed at the pads on the chip, and the second bonding is applied to part overlying the metal balls.